A Study of Signal Integrity Issues in Through-Silicon-Via-based 3D ICs

Abstract-In this paper, we study the signal integrity issues of throughsilicon-via (TSV)-based 3D IC layouts. Unlike the most existing work, our study reports the coupling noise among all nets and all TSVs used in a real processor design implemented in 3D. Our RTL-to-GDSII design flow consists of commercial tools, enhanced with various add-ons to handle TSV and 3D stacking. Using this tool flow, we generate GDSII-level layouts of 3D implementation and perform sign-off-level signal integrity analysis. Based on our 2D vs 3D GDSII comparisons, we found that the overall noise-level of 3D is worse than 2D, but 3D designs have the advantage of significantly reducing the total number of the nosiest nets

Efficacy of Ronidazole for Treatment of Cats Experimentally Infected with a Korean Isolate of Tritrichomonas foetus

To evaluate the efficacy of ronidazole for treatment of Tritrichomonas foetus infection, 6 Tritrichomonas-free kittens were experimentally infected with a Korean isolate of T. foetus. The experimental infection was confirmed by direct microscopy, culture, and single-tube nested PCR, and all cats demonstrated trophozoites of T. foetus by day 20 post-infection in the feces. From day 30 after the experimentally induced infection, 3 cats were treated with ronidazole (50 mg/kg twice a day for 14 days) and 3 other cats received placebo. Feces from each cat were tested for the presence of T. foetus by direct smear and culture of rectal swab samples using modified Diamond's medium once a week for 4 weeks. To confirm the culture results, the presence of T. foetus rRNA gene was determined by single-tube nested PCR assay. All 3 cats in the treatment group receiving ronidazole showed negative results for T. foetus infection during 2 weeks of treatment and 4 weeks follow-up by all detection methods used in this study. In contrast, rectal swab samples from cats in the control group were positive for T. foetus continuously throughout the study. The present study indicates that ronidazole is also effective to treat cats infected experimentally with a Korean isolate of T. foetus at a dose of 50 mg/kg twice a day for 14 days

ILP-based Supply and Threshold Voltage Assignment For Total Power Minimization

In this paper we present an ILP-based method to simultaneously assign supply and threshold voltages to individual gates for dynamic and leakage power minimization. In our three-step approach, low power min-flipflop (FF) retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage assignment formulated in ILP makes the best possible supply/threshold voltage assignment under the given clock period constraint set by the retiming. Finally, a post-process further refines the voltage assignment solution by exploiting the remaining timing slack in the circuit. Related experiments show that the min-FF retiming plus simultaneous Vdd/Vth assignment approach outperforms the existing max-FF retiming plus Vdd-only assignment approach

Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs

Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We derive a new 3D wirelength distri-bution model considering TSV size. Based on this new prediction model, we explain the impact of several design parameters newly introduced in 3D ICs. We also present a case study to show how the model can help make early design decisions for 3D ICs

In situ electrochemical surface modification for high-voltage LiCoO2 in lithium ion batteries

High-voltage LiCoO2 has been revisited to improve the energy density of lithium ion batteries. LiCoO2 can deliver the reversible capacity of about 200 mA h g(-1) when the upper cut-off voltage increases to 4.55 V (vs. Li/Li+). However, the high upper cut-off voltage causes the severe failures of LiCoO2 such as structural degradation, electrolyte decomposition, and Co dissolution. Various surface-modified LiCoO2 materials have been introduced to suppress electrolyte decomposition and Co dissolution, thereby leading to the improved electrochemical performance. Most of the coated LiCoO2 materials are obtained through a conventional coating process such as sol-gel synthesis, which is complex and high-cost. In this paper, the in situ electrochemical coating method is introduced as a simple and low-cost coating process, where the electrolyte additive of Mg salts is electrochemically decomposed to form a MgF2-based coating layer on the LiCoO2 surface. LiCoO2 electrochemically coated with MgF2 suppresses Co dissolution in electrolytes, resulting in excellent electrochemical performance such as high reversible capacity of 198 mA h g(-1) and stable cycle performance over 100 cycles in the voltage range between 3 and 4.55 V (vs. Li/Li+) at 45 degrees C. The formation mechanism of MgF2 is also demonstrated through ex situ XPS and XANES analyses.

Impact of Multi-level Clustering on Performance Driven Global Placement

Delay and wirelength minimization continue to be important objectives in the design of high-performance computing systems. For large-scale circuits, the clustering process becomes essential for reducing the problem size. However, to the best of our knowledge, there is no study about the impact of multi-level clustering on performance-driven global placement. In this paper, five clustering algorithms including the quasi-optimal retiming delay driven PRIME and the cutsize-driven ESC have been considered for their impact on state-of-the-art mincut based global placement. Results show that minimizing cutsize or wirelength during clustering typically results in significant performance improvements

Through-silicon-via management during 3D physical design: When to add and how many?

Abstract — In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods. I